From energy-delay metrics to constraints on the design of digital circuits

In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energyefficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of Ei D j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing Ei D j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results. Copyright 2011 John Wiley & Sons, Ltd.